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ARM Instruction Set Architecture (ISA) - Overview

General Classification of Instructions

• Data Movement

• Arithmetic

• Logical

• Shift

• Program Control

Updating ARM Condition Codes

• ARM will only update the condition codes when specifically called for by the instruction.

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  ADDS r1, r2, r3       @ 'S' calls for an update in the condition codes
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  ADD  r1, r2, r3       @ Will not update the condition codes
  

ARM Data Processing, Data Transfer, and Compare Instructions

• Remember! This only tells a part of the story. For more information, see ARM Assembly Language Reference Card.

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  Instruction               ARM Mnemonic        Definition (RTL)
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  ========================  ==================  ============================
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  Addition                  ADD r0, r1, r2      [r0] ← [r1] + [r2]
  4
  Subtraction               SUB r0, r1, r2      [r0] ← [r1] - [r2]
  5
  AND                       AND r0, r1, r2      [r0] ← [r1] · [r2]
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  OR                        ORR r0, r1, r2      [r0] ← [r1] + [r2]
  7
  Exclusive OR              EOR r0, r1, r2      [r0] ← [r1] ⊕ [r2]
  8
  Multiply                  MUL r0, r1, r2      [r0] ← [r1] x [r2]
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  Register-register move    MOV r0, r1          [r0] ← [r1]
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  Compare                   CMP r1, r2          [r1] - [r2]
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  Branch on zero to label   BEQ label           [PC] ← label (jump to label)