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ARM Thumb Instruction Set Architecture (ISA)

 

Compressed Code, RISC, Thumb and MIPS-16

 

ARM Thumb ISA

 

the-thumb-register-set

 

Design Decisions

Other Design Decisions

Thumb-state Data Processing Instructions

 

encoding-the-thumb-state-data-processing-instructions

 

Thumb-state Branch Instructions

 

encoding-the-thumb-mode-branch-instructions

 

Switching to ARM Thumb Mode

Thumb-state Load and Store Instructions

 

encoding-the-thumb-state-data-transfer-instructions

 

Thumb-state Multiple Move Instructions

 

encoding-the-thumb-mode-multiple-register-transfer-instructions

 

 

What Else Does Change in Thumb Mode?

 

Why Do We Study Thumb Mode?

 

Mr. Preston's Experiences with Thumb Mode

  1. Auto-indexing did NOT work!

    • Use Indirect Addressing instead, and manually update the reference (index) register.

  2. LDR did NOT work with r8|r9|r10.

    • MOV did work fine with the higher-order registers.

  3. MUL operands:

    And all operand registers had to be lower-order registers; r0-r7.

  4. For lr, PUSH only!, for pc, POP only!

  5. UMULL did work in Thumb mode even though it is said that it is not supported in 16-bit mode. Had no issues using higher-order registers during compilation. But, at runtime, only lower-order registers r0-r7 were allowed.

    • When higher-order registers were used segmentation fault!

  6. LDRB, STRB (for printf and scanf in bytes) did not work. Needs some investigation!