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ARM's Load & Store Encoding

ARM's Load & Store Encoding

• The LDR and STR can have conditional execution.

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  5
  1
  @ if (a == b) { x = p; } else { x = q; }
  2
  
  3
  CMP   r1, r2
  4
  LDREQ r3, [r4]
  5
  LDRNE r3, [r5]
  

• Not sure if the addition or subtraction of an offset is part of these two instructions only or it is just discussed only here in the text.

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  LDR r0, [r1, +r2]
  2
  LDR r0, [r1, -r2]     @ Pre-indexed; the base register r1 is NOT updated.
  

• If you need to access a byte in memory, the LDR and STR (and only these two) support that with adding a "B" to the instruction.

  Default is to access 32-bit word.

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  STRB r0, [r2]
  2
  LDRB r1, [r1]
  

  This is necessary if you need to parse a string to look at each byte (character) at a time, or limit the user input using %s versus %c.