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The Stored Program Concept

Fundamental Action of a Stored Program Machine

• Program execution cycle expressed in pseudocode

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  /* Stored program machine */
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      Point to the first instruction in memory
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      REPEAT
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          Read the instruction at the memory location pointed at
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          Point to the next instruction
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          Decode the instruction read from memory
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          Execute the instruction
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      FOREVER
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  End
  

• Execute the instruction step in detail (in pseudocode)

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  /* Execute the instruction */
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      IF the instruction requires data
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          THEN fetch the data from memory
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      END_IF
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      Perform the operation defined by the instruction
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      IF the instruction requires data to be stored in memory
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          THEN store the data in memory
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      END_IF
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  End
  

• Program execution cycle expressed in C

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  ProgramCounter = 0;                         // point to the 1st instruction
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  do
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  {
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      instruction = memory[ProgramCounter];   // read the instruction
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      updatepc(ProgramCounter);               // pc point to next instruction
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      decode(instruction);                    // decode the instruction
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      fetch(operands);                        // fetch required data
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      execute;                                // execute the instruction
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      store(results);                         // store the result
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  } while (instruction != terminate);
  

• Stored program machines require two memory access per instruction.

  • One to read the instruction from memory.

  • The other to either read data from memory that is required by the current instruction or to put data in memory that previously has been created or modified in the CPU by an earlier instruction.

  • The term von Neumann bottleneck indicates that one of the problems of the stored program computer is the path between the CPU and the memory.

    • Harvard Architecture solves this issue by using separate storages and buses for data and instructions.

• Store program machines are said to operate in a two-phase mode called a fetch/execute cycle.

Three Address (Operand) Instructions

• Format

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  Operation Address1, Address2, Address3
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  (Operation Destination, Source1, Source2)
  

  Operation specifies the action the instruction is to carry out (e.g., add, subtrace, multiply, etc.) and Address1, Address2, Address3 are the locations of the three operands in memory.

  There is a standard for the way in which the sequence of operands is written. Different computers may use the different notation.

• Equivalent RTL Notation

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  [Address1] ← [Address2] Operation [Address3]
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  ([Destination] ← [Source1] Operation [Source2])
  

• Example

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  ADD P, Q, R
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  [P] ← [Q] + [R] // in RTL notation
  

  ADD P, Q, R is the symbolic form of the actual instruction that would be stored in memory as a binary sequence of 1s and 0s, meaning "add the contents of Q to the contents of R and put the result in P".

  P, Q, and R are the symbolic names of the addresses of three memory locations.

  This operation requires four memory accesses (e.g., one to fetch the instruction, two to fetch the two source operands, and one to store the result).

  Here ADD is called an op-code (abbreviated from operation code ). An op-code is the portion of a machine language instruction that specifies the operation to be performed.

   

Two Address (Operand) Instructions

• Format

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  Operation Address1, Address2
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  (Operation Destination, Source1)
  

  Address2 is a source operand and Address1 is both a source and a destination operand.

  The source operand Address1 is replaced (overwritten) by the result.

  Practical computers do not generally allow you to use two memory addresses in the same instruction. Most computers specify one address in memory and a second address as a register.

• Equivalent RTL Notation

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  [Address1] ← [Address1] Operation [Address2]
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  ([Destination] ← [Destination] Operation [Source])
  

• Example

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  ADD P, Q
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  [P] ← [P] + [Q] // in RTL notation
  

One Address (Operand) Instructions

• Format

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  1
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  Operation address
  

• Example

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  LOAD    Q   (Read Q into the accumulator)
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  ADD     R   (Add R to the accumulator)
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  STORE   P   (Store the accumulator in P)
  

  Above instructions simply mean P = Q + R.

  Because only one address is provided and at least two addresses are required, the processor has to use an operand that doesn't require an explicit address (Q in this example). That is, this operand comes from a register once called the accumulator within the CPU.

  In some cases, accumulator acts as a bottleneck, because all of the data has to flow through it.

Addressing Mode

• Addressing modes are an aspect of the instruction set architecture in most CPU designs.

• The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions in that architecture identify the operand(s) of each instruction.

• An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

• Examples

  • Location of an operand given directly (i.e., it's in location 1000).

  • Location of an operand given indirectly (i.e., register 6 contains the address of the operand we need).

Computer Categories

Computers can be classified by the way in which their instructions act on data.

• Memory-to-memory

  • Instructions can read source operands from memory, perform an operation on the data, and store (return) the result in memory.

  • These types of computers (CPUs) do not even require the use of registers to execute instructions.

• Register-to-register

  • Computers that perform operations only on the contents of registers.

  • Also called, load/store computers since LOAD and STORE operations are the only memory access instructions provided.

    • LOAD instruction must be used to put the data in registers.

    • STORE instruction must be used to transfer data from a register to memory.

  • Falls into the class of RISC

  • e.g., ARM, MIPS

• Register-to-memory

  • Computers that can perform operations on two operands where one is in memory and the other in a register (the result is written to either memory or a register).

  • Falls into the class of CISC

  • e.g., Intel IA32 (8086, Pentium, Core i7)