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Device Header File (stm32f407xx.h)

Device Header File

• A device header file (C header file in this case) is a header file which contains MCU specific details such as:

  • Base addresses of various memories present in the MCU such as Flash, SRAM1, SRAM2, ROM, etc.

  • Base addresses of various bus domains such as AHBx domain, APBx domain, etc.

  • Base addresses of various peripherals present in different bus domains of the MCU.

  • Clock management macros (i.e., clock enable/disable macros)

  • IRQ definitions

  • Peripheral register definition structures

  • Peripheral register bit definitions

  • Other useful MCU configuration macros

• The device header file will be used by both the application and the drivers. Therefore, the application and the driver source files may #include the device specific header file to access MCU specific details.

Code

stm32f407xx.h

Path: Project/Drivers/Inc/

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/*******************************************************************************
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 * File     : stm32f407xx.h
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 * Brief    : Device header file for stm32f407xx MCU
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 * Author   ; Kyungjae Lee
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 * Date     : May 18, 2023
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 *
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 * Note     : This code includes only the features that are necessary for my
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 *            personal projects.
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 * ****************************************************************************/
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#ifndef STM32F407XX_H
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#define STM32F407XX_H
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#include <stdint.h>
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#include <stddef.h> /* NULL */
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#define __IO            volatile        /* I/O registers are highly volatile */
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#define __WEAK          __attribute__((weak))
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/********************* START: Processor Specific Details **********************/
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/**
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 * ARM Cortex-Mx processor NVIC_ISERx register addresses
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 * Interrupt Set-enable Registers
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 * Note: Since ARM Cortex-Mx process implements only 82 interrupts, ISER3-7 will
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 *       not be used.
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 *       NVIC could be defined as a structure, but just the necessary registers
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 *       are defined separately here since there is too much space in between
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 *       each group of registers.
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 */
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#define NVIC_ISER0      ((uint32_t volatile *)0xE000E100)
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#define NVIC_ISER1      ((uint32_t volatile *)0xE000E104)
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#define NVIC_ISER2      ((uint32_t volatile *)0xE000E108)
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#define NVIC_ISER3      ((uint32_t volatile *)0xE000E10C)
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#define NVIC_ISER4      ((uint32_t volatile *)0xE000E110)
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#define NVIC_ISER5      ((uint32_t volatile *)0xE000E114)
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#define NVIC_ISER6      ((uint32_t volatile *)0xE000E118)
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#define NVIC_ISER7      ((uint32_t volatile *)0xE000E11C)
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/**
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 * ARM Cortex-Mx processor NVIC_ICERx register addresses
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 * Interrupt Clear-enable Registers
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 * Note: Since ARM Cortex-Mx process implements only 82 interrupts, ISER3-7 will
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 *       not be used.
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 *       NVIC could be defined as a structure, but just the necessary registers
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 *       are defined separately here since there is too much space in between
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 *       each group of registers.
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 */
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#define NVIC_ICER0      ((uint32_t volatile *)0XE000E180)
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#define NVIC_ICER1      ((uint32_t volatile *)0xE000E184)
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#define NVIC_ICER2      ((uint32_t volatile *)0xE000E188)
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#define NVIC_ICER3      ((uint32_t volatile *)0xE000E18C)
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#define NVIC_ICER4      ((uint32_t volatile *)0xE000E190)
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#define NVIC_ICER5      ((uint32_t volatile *)0xE000E194)
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#define NVIC_ICER6      ((uint32_t volatile *)0xE000E198)
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#define NVIC_ICER7      ((uint32_t volatile *)0xE000E19C)
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/**
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 * ARM Cortex-Mx processor NVIC_IPRx register addresses
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 * Interrupt Priority Registers
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 * Note: NVIC could be defined as a structure, but just the necessary registers
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 *       are defined separately here since there is too much space in between
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 *       each group of registers.
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 */
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#define NVIC_IPR_BASE   ((uint32_t volatile *)0xE000E400)
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#define NUM_PRI_BITS_USED   4
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/*********************** END: Processor Specific Details **********************/
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/* Base addresses of memories */
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#define FLASH_BASE      0x08000000U     /* Flash base address in the alias              */
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#define SRAM1_BASE      0x20000000U     /* SRAM1(112 KB) base address in the alias      */
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#define SRAM2_BASE      0x20001C00U     /* SRAM2(16 KB) base address in the alias       */
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#define SRAM_BASE       SRAM1_BASE      /* SRAM base address in the alias               */
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#define ROM_BASE        0x1FFF0000U     /* ROM(system memory) base address in the alias */
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/* Base addresses of APBx and AHB bus peripherals */
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#define PERIPH_BASE     0x40000000U     /* Peripheral base address in the alias         */
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#define APB1PERIPH_BASE PERIPH_BASE
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#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
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#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
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#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
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/* Base addresses of AHB1 peripherals */
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#define GPIOA_BASE      (AHB1PERIPH_BASE + 0x0000U)
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#define GPIOB_BASE      (AHB1PERIPH_BASE + 0x0400U)
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#define GPIOC_BASE      (AHB1PERIPH_BASE + 0x0800U)
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#define GPIOD_BASE      (AHB1PERIPH_BASE + 0x0C00U)
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#define GPIOE_BASE      (AHB1PERIPH_BASE + 0x1000U)
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#define GPIOF_BASE      (AHB1PERIPH_BASE + 0x1400U)
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#define GPIOG_BASE      (AHB1PERIPH_BASE + 0x1800U)
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#define GPIOH_BASE      (AHB1PERIPH_BASE + 0x1C00U)
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#define GPIOI_BASE      (AHB1PERIPH_BASE + 0x2000U)
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#define RCC_BASE        (AHB1PERIPH_BASE + 0x3800U)
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/* Base addresses of APB1 peripherals */
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#define SPI2_BASE       (APB1PERIPH_BASE + 0x3800U)
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#define SPI3_BASE       (APB1PERIPH_BASE + 0x3C00U)
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#define USART2_BASE     (APB1PERIPH_BASE + 0x4400U)
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#define USART3_BASE     (APB1PERIPH_BASE + 0x4800U)
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#define UART4_BASE      (APB1PERIPH_BASE + 0x4C00U)
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#define UART5_BASE      (APB1PERIPH_BASE + 0x5000U)
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#define I2C1_BASE       (APB1PERIPH_BASE + 0x5400U)
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#define I2C2_BASE       (APB1PERIPH_BASE + 0x5800U)
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#define I2C3_BASE       (APB1PERIPH_BASE + 0x5C00U)
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/* Base addresses of APB2 peripherals */
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#define USART1_BASE     (APB2PERIPH_BASE + 0x1000U)
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#define USART6_BASE     (APB2PERIPH_BASE + 0x1400U)
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#define SPI1_BASE       (APB2PERIPH_BASE + 0x3000U)
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#define SPI4_BASE       (APB2PERIPH_BASE + 0x3400U)
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#define SYSCFG_BASE     (APB2PERIPH_BASE + 0x3800U)
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#define EXTI_BASE       (APB2PERIPH_BASE + 0x3C00U)
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/**
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 * Peripheral registers structures
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 *
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 * Note: Number of registers of each peripheral may defer from MCU family to MCU
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 *       family. Check the reference manual!
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 */
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/* General Purpose I/O */
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typedef struct
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{
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    __IO uint32_t MODER;    /* GPIO port mode register,                 Address offset: 0x00        */
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    __IO uint32_t OTYPER;   /* GPIO port output type register,          Address offset: 0x04        */
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    __IO uint32_t OSPEEDR;  /* GPIO port output speed register,         Address offset: 0x08        */
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    __IO uint32_t PUPDR;    /* GPIO port pull-up/pull-down register,    Address offset: 0x0C        */
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    __IO uint32_t IDR;      /* GPIO port input data register,           Address offset: 0x10        */
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    __IO uint32_t ODR;      /* GPIO port output data register,          Address offset: 0x14        */
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    __IO uint32_t BSRR;     /* GPIO port bit set/reset register,        Address offset: 0x18        */
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    __IO uint32_t LCKR;     /* GPIO port configuration lack register,   Address offset: 0x1C        */
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    __IO uint32_t AFR[2];   /* GPIO port alternate function register,   Address offset: 0x20-0x24   */
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} GPIO_TypeDef;
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/* Reset and Clock Control */
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typedef struct
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{
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    __IO uint32_t CR;           /* RCC clock control register,                                  Address offset: 0x00 */
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    __IO uint32_t PLLCFGR;      /* RCC PLL configuration register,                              Address offset: 0x04 */
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    __IO uint32_t CFGR;         /* RCC clock configuration register,                            Address offset: 0x08 */
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    __IO uint32_t CIR;          /* RCC clock interrupt register,                                Address offset: 0x0C */
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    __IO uint32_t AHB1RSTR;     /* RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
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    __IO uint32_t AHB2RSTR;     /* RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
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    __IO uint32_t AHB3RSTR;     /* RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
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    uint32_t     RESERVED0;     /* Reserved, Address offset: 0x1C                                                    */
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    __IO uint32_t APB1RSTR;     /* RCC APB1 peripheral reset register,                          Address offset: 0x20 */
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    __IO uint32_t APB2RSTR;     /* RCC APB2 peripheral reset register,                          Address offset: 0x24 */
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    uint32_t     RESERVED1[2];  /* Reserved, Address offset: 0x28-0x2C                                               */
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    __IO uint32_t AHB1ENR;      /* RCC AHB1 peripheral clock enable register,                   Address offset: 0x30 */
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    __IO uint32_t AHB2ENR;      /* RCC AHB2 peripheral clock enable register,                   Address offset: 0x34 */
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    __IO uint32_t AHB3ENR;      /* RCC AHB3 peripheral clock enable register,                   Address offset: 0x38 */
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    uint32_t     RESERVED2;     /* Reserved, Address offset: 0x3C                                                    */
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    __IO uint32_t APB1ENR;      /* RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
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    __IO uint32_t APB2ENR;      /* RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
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    uint32_t     RESERVED3[2];  /* Reserved, Address offset: 0x48-0x4C                                               */
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    __IO uint32_t AHB1LPENR;    /* RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
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    __IO uint32_t AHB2LPENR;    /* RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
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    __IO uint32_t AHB3LPENR;    /* RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
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    uint32_t     RESERVED4;     /* Reserved, Address offset: 0x04                                                    */
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    __IO uint32_t APB1LPENR;    /* RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
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    __IO uint32_t APB2LPENR;    /* RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
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    uint32_t     RESERVED5[2];  /* Reserved, Address offset: 0x68-0x6C                                               */
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    __IO uint32_t BDCR;         /* RCC Backup domain control register,                              Address offset: 0x70 */
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    __IO uint32_t CSR;          /* RCC clock control & status register,                             Address offset: 0x74 */
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    uint32_t     RESERVED6[2];  /* Reserved, Address offset: 0x78-7C                                                 */
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    __IO uint32_t SSCGR;        /* RCC spread spectrum clock generation register,               Address offset: 0x80 */
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    __IO uint32_t PLLI2SCFGR;   /* RCC PLLI2S configuration register,                               Address offset: 0x84 */
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} RCC_TypeDef;
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/* External interrupt/event controller (EXTI) */
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typedef struct
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{
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    __IO uint32_t IMR;      /* Interrupt mask register,             Address offset: 0x00 */
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    __IO uint32_t EMR;      /* Event mask register,                 Address offset: 0x04 */
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    __IO uint32_t RTSR;     /* Rising trigger selection register,   Address offset: 0x08 */
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    __IO uint32_t FTSR;     /* Falling trigger selection register,  Address offset: 0x0C */
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    __IO uint32_t SWIER;    /* Software interrupt event register,   Address offset: 0x10 */
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    __IO uint32_t PR;       /* Pending register,                    Address offset: 0x14 */
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} EXTI_TypeDef;
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/* System configuration controller (SYSCFG) */
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typedef struct
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{
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    __IO uint32_t MEMRMP;   /* SYSCFG memory remap register,                        Address offset: 0x00 */
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    __IO uint32_t PMC;      /* SYSCFG peripheral mode configuration register,       Address offset: 0x04 */
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    __IO uint32_t EXTICR[4];/* SYSCFG external interrupt configuration register1-4, Address offset: 0x08 */
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    uint32_t RESERVED[2];   /* Reserved, Address offset: 0x18-0x1C                                       */
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    __IO uint32_t CMPCR;    /* Compensation cell control register,                  Address offset: 0x20 */
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} SYSCFG_TypeDef;
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/* Serial peripheral interface (SPI) */
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typedef struct
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{
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    __IO uint32_t CR1;      /* SPI control register 1,              Address offset: 0x00 */
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    __IO uint32_t CR2;      /* SPI control register 2,              Address offset: 0x04 */
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    __IO uint32_t SR;       /* SPI status register,                 Address offset: 0x08 */
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    __IO uint32_t DR;       /* SPI data register,                   Address offset: 0x0C */
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    __IO uint32_t SRCPR;    /* SPI CRC polynomial register,         Address offset: 0x10 */
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    __IO uint32_t RXCRCR;   /* SPI RX CRC register,                 Address offset: 0x14 */
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    __IO uint32_t TXCRCR;   /* SPI TX CRC register,                 Address offset: 0x18 */
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    __IO uint32_t I2SCFGR;  /* SPI_I2S configuration register,      Address offset: 0x1C */
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    __IO uint32_t I2SPR;    /* SPI_I2S prescaler register,          Address offset: 0x20 */
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} SPI_TypeDef;
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/* Inter-integrated circuit (I2C) */
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typedef struct
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{
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    __IO uint32_t CR1;      /* I2C control register 1,              Address offset: 0x00 */
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    __IO uint32_t CR2;      /* I2C control register 2,              Address offset: 0x04 */
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    __IO uint32_t OAR1;     /* I2C own address register,            Address offset: 0x08 */
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    __IO uint32_t OAR2;     /* I2C own address register,            Address offset: 0x0C */
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    __IO uint32_t DR;       /* I2C data register,                   Address offset: 0x10 */
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    __IO uint32_t SR1;      /* I2C status register,                 Address offset: 0x14 */
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    __IO uint32_t SR2;      /* I2C status register,                 Address offset: 0x18 */
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    __IO uint32_t CCR;      /* I2C clock control register,          Address offset: 0x1C */
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    __IO uint32_t TRISE;    /* I2C TRISE register,                  Address offset: 0x20 */
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    __IO uint32_t FLTR;     /* I2C FLTR register,                   Address offset: 0x24 */
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} I2C_TypeDef;
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/* Universal synchronous asynchronous receiver transmitter (USART) */
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typedef struct
226
{
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    __IO uint32_t SR;       /* USART status register,                   Address offset: 0x00 */
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    __IO uint32_t DR;       /* USART data register,                     Address offset: 0x04 */
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    __IO uint32_t BRR;      /* USART baud rate register,                Address offset: 0x08 */
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    __IO uint32_t CR1;      /* USART control register 1,                Address offset: 0x0C */
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    __IO uint32_t CR2;      /* USART control register 2,                Address offset: 0x10 */
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    __IO uint32_t CR3;      /* USART control register 3,                Address offset: 0x14 */
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    __IO uint32_t GTPR;     /* USART guard time and prescalar register, Address offset: 0x18 */
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} USART_TypeDef;
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/**
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 * Peripheral declarations (Peripheral base addresses typecasted to
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 * (x_TypeDef *))
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 */
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/* GPIOs */
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#define GPIOA           ((GPIO_TypeDef *)GPIOA_BASE)
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#define GPIOB           ((GPIO_TypeDef *)GPIOB_BASE)
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#define GPIOC           ((GPIO_TypeDef *)GPIOC_BASE)
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#define GPIOD           ((GPIO_TypeDef *)GPIOD_BASE)
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#define GPIOE           ((GPIO_TypeDef *)GPIOE_BASE)
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#define GPIOF           ((GPIO_TypeDef *)GPIOF_BASE)
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#define GPIOG           ((GPIO_TypeDef *)GPIOG_BASE)
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#define GPIOH           ((GPIO_TypeDef *)GPIOH_BASE)
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#define GPIOI           ((GPIO_TypeDef *)GPIOI_BASE)
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/* RCC */
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#define RCC             ((RCC_TypeDef *)RCC_BASE)
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/* EXTI */
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#define EXTI            ((EXTI_TypeDef *)EXTI_BASE)
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/* SYSCFG */
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#define SYSCFG          ((SYSCFG_TypeDef *)SYSCFG_BASE)
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/* SPIx */
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#define SPI1            ((SPI_TypeDef *)SPI1_BASE)
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#define SPI2            ((SPI_TypeDef *)SPI2_BASE)
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#define SPI3            ((SPI_TypeDef *)SPI3_BASE)
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#define SPI4            ((SPI_TypeDef *)SPI4_BASE)
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/* I2Cx */
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#define I2C1            ((I2C_TypeDef *)I2C1_BASE)
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#define I2C2            ((I2C_TypeDef *)I2C2_BASE)
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#define I2C3            ((I2C_TypeDef *)I2C3_BASE)
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/* USARTx */
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#define USART1          ((USART_TypeDef *)USART1_BASE)
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#define USART2          ((USART_TypeDef *)USART2_BASE)
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#define USART3          ((USART_TypeDef *)USART3_BASE)
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#define UART4           ((USART_TypeDef *)UART4_BASE)
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#define UART5           ((USART_TypeDef *)UART5_BASE)
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#define USART6          ((USART_TypeDef *)USART6_BASE)
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/**
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 * Clock enable macros for peripherals
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 */
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/* GPIOx */
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#define GPIOA_PCLK_EN()     (RCC->AHB1ENR |= (1 << 0))
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#define GPIOB_PCLK_EN()     (RCC->AHB1ENR |= (1 << 1))
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#define GPIOC_PCLK_EN()     (RCC->AHB1ENR |= (1 << 2))
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#define GPIOD_PCLK_EN()     (RCC->AHB1ENR |= (1 << 3))
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#define GPIOE_PCLK_EN()     (RCC->AHB1ENR |= (1 << 4))
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#define GPIOF_PCLK_EN()     (RCC->AHB1ENR |= (1 << 5))
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#define GPIOG_PCLK_EN()     (RCC->AHB1ENR |= (1 << 6))
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#define GPIOH_PCLK_EN()     (RCC->AHB1ENR |= (1 << 7))
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#define GPIOI_PCLK_EN()     (RCC->AHB1ENR |= (1 << 8))
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/* I2Cx */
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#define I2C1_PCLK_EN()      (RCC->APB1ENR |= (1 << 21))
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#define I2C2_PCLK_EN()      (RCC->APB1ENR |= (1 << 22))
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#define I2C3_PCLK_EN()      (RCC->APB1ENR |= (1 << 23))
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/* SPIx */
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#define SPI1_PCLK_EN()      (RCC->APB2ENR |= (1 << 12))
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#define SPI2_PCLK_EN()      (RCC->APB1ENR |= (1 << 14))
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#define SPI3_PCLK_EN()      (RCC->APB1ENR |= (1 << 15))
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#define SPI4_PCLK_EN()      (RCC->APB2ENR |= (1 << 13))
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/* USARTx */
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#define USART1_PCLK_EN()    (RCC->APB2ENR |= (1 << 4))
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#define USART2_PCLK_EN()    (RCC->APB1ENR |= (1 << 17))
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#define USART3_PCLK_EN()    (RCC->APB1ENR |= (1 << 18))
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#define UART4_PCLK_EN()     (RCC->APB1ENR |= (1 << 19))
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#define UART5_PCLK_EN()     (RCC->APB1ENR |= (1 << 20))
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#define USART6_PCLK_EN()    (RCC->APB2ENR |= (1 << 5))
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/* SYSCFG */
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#define SYSCFG_PCLK_EN()    (RCC->APB2ENR |= (1 << 14))
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319

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/**
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 * Clock enable macros for peripherals
322
 */
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/* GPIOx */
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#define GPIOA_PCLK_DI()     (RCC->AHB1ENR &= ~(1 << 0))
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#define GPIOB_PCLK_DI()     (RCC->AHB1ENR &= ~(1 << 1))
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#define GPIOC_PCLK_DI()     (RCC->AHB1ENR &= ~(1 << 2))
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#define GPIOD_PCLK_DI()     (RCC->AHB1ENR &= ~(1 << 3))
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#define GPIOE_PCLK_DI()     (RCC->AHB1ENR &= ~(1 << 4))
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#define GPIOF_PCLK_DI()     (RCC->AHB1ENR &= ~(1 << 5))
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#define GPIOG_PCLK_DI()     (RCC->AHB1ENR &= ~(1 << 6))
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#define GPIOH_PCLK_DI()     (RCC->AHB1ENR &= ~(1 << 7))
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#define GPIOI_PCLK_DI()     (RCC->AHB1ENR &= ~(1 << 8))
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/* I2Cx */
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#define I2C1_PCLK_DI()      (RCC->APB1ENR &= ~(1 << 21))
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#define I2C2_PCLK_DI()      (RCC->APB1ENR &= ~(1 << 22))
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#define I2C3_PCLK_DI()      (RCC->APB1ENR &= ~(1 << 23))
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/* SPIx */
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#define SPI1_PCLK_DI()      (RCC->APB2ENR &= ~(1 << 12))
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#define SPI2_PCLK_DI()      (RCC->APB1ENR &= ~(1 << 14))
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#define SPI3_PCLK_DI()      (RCC->APB1ENR &= ~(1 << 15))
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#define SPI4_PCLK_DI()      (RCC->APB2ENR |= ~(1 << 13))
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/* USARTx */
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#define USART1_PCLK_DI()    (RCC->APB2ENR &= ~(1 << 4))
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#define USART2_PCLK_DI()    (RCC->APB1ENR &= ~(1 << 17))
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#define USART3_PCLK_DI()    (RCC->APB1ENR &= ~(1 << 18))
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#define UART4_PCLK_DI()     (RCC->APB1ENR &= ~(1 << 19))
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#define UART5_PCLK_DI()     (RCC->APB1ENR &= ~(1 << 20))
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#define USART6_PCLK_DI()    (RCC->APB2ENR &= ~(1 << 5))
353

354
/* SYSCFG */
355
#define SYSCFG_PCLK_DI()    (RCC->APB2ENR &= ~(1 << 14))
356

357

358
/**
359
 * Reset peripherals (set the corresponding bit, and then clear)
360
 */
361

362
/* GPIO */
363
#define GPIOA_RESET()       do { (RCC->AHB1RSTR |= (1 << 0)); (RCC->AHB1RSTR &= ~(1 << 0)); } while (0)
364
#define GPIOB_RESET()       do { (RCC->AHB1RSTR |= (1 << 1)); (RCC->AHB1RSTR &= ~(1 << 1)); } while (0)
365
#define GPIOC_RESET()       do { (RCC->AHB1RSTR |= (1 << 2)); (RCC->AHB1RSTR &= ~(1 << 2)); } while (0)
366
#define GPIOD_RESET()       do { (RCC->AHB1RSTR |= (1 << 3)); (RCC->AHB1RSTR &= ~(1 << 3)); } while (0)
367
#define GPIOE_RESET()       do { (RCC->AHB1RSTR |= (1 << 4)); (RCC->AHB1RSTR &= ~(1 << 4)); } while (0)
368
#define GPIOF_RESET()       do { (RCC->AHB1RSTR |= (1 << 5)); (RCC->AHB1RSTR &= ~(1 << 5)); } while (0)
369
#define GPIOG_RESET()       do { (RCC->AHB1RSTR |= (1 << 6)); (RCC->AHB1RSTR &= ~(1 << 6)); } while (0)
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#define GPIOH_RESET()       do { (RCC->AHB1RSTR |= (1 << 7)); (RCC->AHB1RSTR &= ~(1 << 7)); } while (0)
371
#define GPIOI_RESET()       do { (RCC->AHB1RSTR |= (1 << 8)); (RCC->AHB1RSTR &= ~(1 << 8)); } while (0)
372

373
/* SPI */
374
#define SPI1_RESET()        do { (RCC->APB2RSTR |= (1 << 12)); (RCC->APB2RSTR &= ~(1 << 12)); } while (0)
375
#define SPI2_RESET()        do { (RCC->APB1RSTR |= (1 << 14)); (RCC->APB1RSTR &= ~(1 << 14)); } while (0)
376
#define SPI3_RESET()        do { (RCC->APB1RSTR |= (1 << 15)); (RCC->APB1RSTR &= ~(1 << 15)); } while (0)
377
#define SPI4_RESET()        do { (RCC->APB2RSTR |= (1 << 13)); (RCC->APB2RSTR &= ~(1 << 13)); } while (0)
378

379

380
/**
381
 * Macro function to return port code for the given GPIO base address
382
 */
383
#define GPIO_BASE_TO_PORT_CODE(x)   ((x == GPIOA) ? 0 : \
384
                                    (x == GPIOB) ? 1 :  \
385
                                    (x == GPIOC) ? 2 :  \
386
                                    (x == GPIOD) ? 3 :  \
387
                                    (x == GPIOE) ? 4 :  \
388
                                    (x == GPIOF) ? 5 :  \
389
                                    (x == GPIOG) ? 6 :  \
390
                                    (x == GPIOH) ? 7 :  \
391
                                    (x == GPIOI) ? 8 : 0)
392

393

394
/**
395
 * Interrupt Request (IRQ) numbers of STM32F407xx MCU
396
 * Note: This information is specific to MCU family
397
 */
398

399
/* GPIO interrupts */
400
#define IRQ_NO_EXTI0        6
401
#define IRQ_NO_EXTI1        7
402
#define IRQ_NO_EXTI2        8
403
#define IRQ_NO_EXTI3        9
404
#define IRQ_NO_EXTI4        10
405
#define IRQ_NO_EXTI9_5      23
406
#define IRQ_NO_EXTI15_10    40
407

408
/* SPI interrupts */
409
#define IRQ_NO_SPI1         35
410
#define IRQ_NO_SPI2         36
411
#define IRQ_NO_SPI3         51
412

413
/* I2C interrupts */
414
#define IRQ_NO_I2C1_EV      31
415
#define IRQ_NO_I2C1_ER      32
416
#define IRQ_NO_I2C2_EV      33
417
#define IRQ_NO_I2C2_ER      34
418
#define IRQ_NO_I2C3_EV      72
419
#define IRQ_NO_I2C3_ER      73
420

421
/* USART interrupts */
422
#define IRQ_NO_USART1       37
423
#define IRQ_NO_USART2       38
424
#define IRQ_NO_USART3       39
425
#define IRQ_NO_UART4        52
426
#define IRQ_NO_UART5        53
427
#define IRQ_NO_USART6       71
428

429

430
/**
431
 * Possible NVIC IRQ priority levels
432
 */
433
#define NVIC_IRQ_PRI0       0
434
#define NVIC_IRQ_PRI1       1
435
#define NVIC_IRQ_PRI2       2
436
#define NVIC_IRQ_PRI3       3
437
#define NVIC_IRQ_PRI4       4
438
#define NVIC_IRQ_PRI5       5
439
#define NVIC_IRQ_PRI6       6
440
#define NVIC_IRQ_PRI7       7
441
#define NVIC_IRQ_PRI8       8
442
#define NVIC_IRQ_PRI9       9
443
#define NVIC_IRQ_PRI10      10
444
#define NVIC_IRQ_PRI11      11
445
#define NVIC_IRQ_PRI12      12
446
#define NVIC_IRQ_PRI13      13
447
#define NVIC_IRQ_PRI14      14
448
#define NVIC_IRQ_PRI15      15
449

450

451
/**
452
 * SPI peripheral bit position definitions
453
 */
454

455
/* SPI_CR1 */
456
#define SPI_CR1_CPHA        0
457
#define SPI_CR1_CPOL        1
458
#define SPI_CR1_MSTR        2
459
#define SPI_CR1_BR          3
460
#define SPI_CR1_SPE         6
461
#define SPI_CR1_LSBFIRST    7
462
#define SPI_CR1_SSI         8
463
#define SPI_CR1_SSM         9
464
#define SPI_CR1_RXONLY      10
465
#define SPI_CR1_DFF         11
466
#define SPI_CR1_CRCNEXT     12
467
#define SPI_CR1_CRCEN       13
468
#define SPI_CR1_BIDIOE      14
469
#define SPI_CR1_BIDIMODE    15
470

471
/* SPI_CR2 */
472
#define SPI_CR2_RXDMAEN     0
473
#define SPI_CR2_TXDMAEN     1
474
#define SPI_CR2_SSOE        2
475
#define SPI_CR2_FRF         4
476
#define SPI_CR2_ERRIE       5
477
#define SPI_CR2_RXNEIE      6
478
#define SPI_CR2_TXEIE       7
479

480
/* SPI_SR */
481
#define SPI_SR_RXNE         0
482
#define SPI_SR_TXE          1
483
#define SPI_SR_CHSIDE       2
484
#define SPI_SR_UDR          3
485
#define SPI_SR_CRCERR       4
486
#define SPI_SR_MODF         5
487
#define SPI_SR_OVR          6
488
#define SPI_SR_BSY          7
489
#define SPI_SR_FRE          8
490

491

492
/**
493
 * I2C peripheral bit position definitions
494
 */
495

496
/* I2C_CR1 */
497
#define I2C_CR1_PE          0
498
#define I2C_CR1_SMBUS       1
499
#define I2C_CR1_SMBTYPE     3
500
#define I2C_CR1_ENARP       4
501
#define I2C_CR1_ENPEC       5
502
#define I2C_CR1_ENGC        6
503
#define I2C_CR1_NOSTRETCH   7
504
#define I2C_CR1_START       8
505
#define I2C_CR1_STOP        9
506
#define I2C_CR1_ACK         10
507
#define I2C_CR1_POS         11
508
#define I2C_CR1_PEC         12
509
#define I2C_CR1_ALERT       13
510
#define I2C_CR1_SWRST       15
511

512
/* I2C_CR2 */
513
#define I2C_CR2_FREQ        0
514
#define I2C_CR2_ITERREN     8
515
#define I2C_CR2_ITEVTEN     9
516
#define I2C_CR2_ITBUFEN     10
517
#define I2C_CR2_DMAEN       11
518
#define I2C_CR2_LAST        12
519

520
/* I2C_OAR1 */
521
#define I2C_OAR1_ADD0       0
522
#define I2C_OAR1_ADD71      1
523
#define I2C_OAR1_ADD98      8
524
#define I2C_OAR1_ADDMODE    15
525

526
/* I2C_SR1 */
527
#define I2C_SR1_SB          0
528
#define I2C_SR1_ADDR        1
529
#define I2C_SR1_BTF         2
530
#define I2C_SR1_ADD10       3
531
#define I2C_SR1_STOPF       4
532
#define I2C_SR1_RxNE        6
533
#define I2C_SR1_TxE         7
534
#define I2C_SR1_BERR        8
535
#define I2C_SR1_ARLO        9
536
#define I2C_SR1_AF          10
537
#define I2C_SR1_OVR         11
538
#define I2C_SR1_PECERR      12
539
#define I2C_SR1_TIMEOUT     14
540
#define I2C_SR1_SMBALERT    15
541

542
/* I2C_SR2 */
543
#define I2C_SR2_MSL         0
544
#define I2C_SR2_BUSY        1
545
#define I2C_SR2_TRA         2
546
#define I2C_SR2_GENCALL     4
547
#define I2C_SR2_SMBDEFAULT  5
548
#define I2C_SR2_SMBDEFAULT  5
549
#define I2C_SR2_SMBHOST     6
550
#define I2C_SR2_DUALF       7
551

552
/* I2C_CCR */
553
#define I2C_CCR_CCR         0
554
#define I2C_CCR_DUTY        14
555
#define I2C_CCR_FS          15
556

557

558
/**
559
 * USART peripheral bit position definitions
560
 */
561

562
/* USART_SR */
563
#define USART_SR_PE             0
564
#define USART_SR_FE             1
565
#define USART_SR_NF             2
566
#define USART_SR_ORE            3
567
#define USART_SR_IDLE           4
568
#define USART_SR_RXNE           5
569
#define USART_SR_TC             6
570
#define USART_SR_TXE            7
571
#define USART_SR_LBD            8
572
#define USART_SR_CTS            9
573

574
/* USART_BRR */
575
#define USART_BRR_DIV_FRACTION  0
576
#define USART_BRR_DIV_MANTISSA  4
577

578
/* USART_CR1 */
579
#define USART_CR1_SBK           0
580
#define USART_CR1_RWU           1
581
#define USART_CR1_RE            2
582
#define USART_CR1_TE            3
583
#define USART_CR1_IDLEIE        4
584
#define USART_CR1_RXNEIE        5
585
#define USART_CR1_TCIE          6
586
#define USART_CR1_TXEIE         7
587
#define USART_CR1_PEIE          8
588
#define USART_CR1_PS            9
589
#define USART_CR1_PCE           10
590
#define USART_CR1_WAKE          11
591
#define USART_CR1_M             12
592
#define USART_CR1_UE            13
593
#define USART_CR1_OVER8         15
594

595
/* USART_CR2 */
596
#define USART_CR2_ADD           0
597
#define USART_CR2_LBDL          5
598
#define USART_CR2_LBDIE         6
599
#define USART_CR2_LBCL          8
600
#define USART_CR2_CPHA          9
601
#define USART_CR2_CPOL          10
602
#define USART_CR2_CLKEN         11
603
#define USART_CR2_STOP          12
604
#define USART_CR2_LINEN         14
605

606
/* USART_CR3 */
607
#define USART_CR3_EIE           0
608
#define USART_CR3_IREN          1
609
#define USART_CR3_IRLP          2
610
#define USART_CR3_HDSEL         3
611
#define USART_CR3_NACK          4
612
#define USART_CR3_SCEN          5
613
#define USART_CR3_DMAR          6
614
#define USART_CR3_DMAT          7
615
#define USART_CR3_RTSE          8
616
#define USART_CR3_CTSE          9
617
#define USART_CR3_CTSIE         10
618
#define USART_CR3_ONEBIT        11
619

620
/* USART_GTPR */
621
#define USART_CR3_PSC           0
622
#define USART_CR3_GT            8
623

624

625
/**
626
 * RCC peripheral bit position definitions
627
 * (Required bit positions only)
628
 */
629
#define RCC_CFGR_SWS        2   /* System clock switch status */
630
#define RCC_CFGR_HPRE       4   /* AHB prescalar */
631
#define RCC_CFGR_PPRE1      10  /* APB low-speed prescalar (APB1) */
632
#define RCC_CFGR_PPRE2      13  /* APB high-speed prescalar (APB2) */
633

634

635
/**
636
 * Other generic macros
637
 */
638
#define ENABLE              1
639
#define DISABLE             0
640
#define SET                 1
641
#define RESET               0
642
#define GPIO_PIN_SET        SET
643
#define GPIO_PIN_RESET      RESET
644
#define I2C_REPEATED_START_EN   ENABLE
645
#define I2C_REPEATED_START_DI   DISABLE
646

647

648
#include "stm32f407xx_rcc_driver.h"
649
#include "stm32f407xx_gpio_driver.h"
650
#include "stm32f407xx_spi_driver.h"
651
#include "stm32f407xx_i2c_driver.h"
652
#include "stm32f407xx_usart_driver.h"
653

654

655
#endif /* STM32F407XX_H */